The field of application of the invention concerns high speed data exchange (in the order of several megabyte/s) among a multiplicity of data processing modules. More precisely, the invention concerns structured transmission systems in which communication between the two processing modules is effected by exchanges of protocol data units (or PDU).
By processing module is understood any type of equipment likely to transmit or receive data, such as an electronic card, a terminal, even a local network segment.
The invention may be applied in particular to all packet transmission systems (system implementing a level 3 procedure, according to the seven level OSI standardisation model), but also to transmission by frame (level 2 ) or transport protocol data units (level 4). More generally, the invention may be applied to any type of transmission system of whatever level (in accordance with the terminology of the OSI standards) of the communication protocol associated with the system in question.
A special field of application of the invention is that of wide band systems, and especially the ATM networks (Asynchronous Transfer Mode (asynchronous transfer method)). In fact, from a technological point of view, the trend towards high speeds would seem to favour the ATM technique, and more generally the `fast packet` technologies', as opposed to the traditional TDM (Time Division Multiplex (multiplexing by division of time)).
The majority of known techniques enable structured data exchange at high speed based on the use of a single shared bus, access to the bus being controlled by algorithms of varying degrees of complexity. These techniques are known under the generic term of timed switching.
Crossbar switching is an alternative to timed switching.
This method is currently implemented in low speed exchange systems, and especially in classic telephone communication (switched telephone network, or RTC). In these systems, a fixed itinerary is allocated to a communication, using means of switching, generally called switching matrices. Classically, a switching matrix enables any input line to be linked with any output line.
In general, crossbar switching techniques are limited to low or average speed applications (below 2 Mb/s) and/or require a single physical line to be reserved for a relatively long period. In fact, they are penalized, in the first analysis, firstly by arbitration problems, especially when two modules want to simultaneously transmit data to the same destination module, and secondly, by problems in arbitration and switching time in making a connection. These two inconveniences would seem to be incompatible with very high speed exchange packet applications.
However, work has been carried out in this field. It is thus that the document `Design and Evaluation of a Distributed Asynchronous VLSI Crossbar Switch Controller for a Packet Switched Supercompter Network` (DuBois and Rasure, Computer Architecture News, June 1991), presents packet switch nodes implementing crossbar matrices for high speed exchanges. This system has proved to be particularly complex, especially regarding arbitration between different requests.
In effect it calls on a distributed arbitration technique, each module capable of transmitting or distributing data including its own means of arbitration (`DACC`). Each of these means of arbitration must therefore be linked independently to all of the other processing modules likely to want to send it data by means of a parallel bus (for example, on 8 bits). Once the number of these modules increases, the system becomes very complex, especially in relation to connections.
It is not difficult to imagine that such a technique, which would seem necessary to function at very high speed, will lead to complex system architecture, and therefore to high manufacture and running costs. This complexity limits the use of such systems with `supercompter` networks.
Furthermore, the already known switching systems are generally handicapped by blockages due to the unavailability of the destination processing module. In effect, each processing module places the data to be transmitted in an FIFO memory. When data has to be switched to an exit already engaged in a transfer, the transmitting module has to wait until transfer is possible. Subsequent data also has to wait, even if their destination exit is free.
The consequence of this phenomenon, called `HOL (Head of Line) blocking` is to reduce the overall output of the switch.